This invention relates to equipment for monitoring synchronous digital logic systems, particularly to logic analyzers having the ability to monitor and selectively acquire data from a synchronous computer system which is undergoing testing.
The field of computer testing equipment includes the use of logic analyzers to assist in the analysis of computer system malfunctions. In the performance of this function, an analyzer is connected to the synchronous logic circuitry of a system under test where it can monitor the status of system hardware and software by observing the operation of the aforementioned circuitry. Normally such circuitry includes, separately or in combination, the address, data, or control busses of the system, circuitry associated with the busses, or the computer itself. Logic analyzers of this type are well-known, the P1540 logic analysis system manufactured by Paratronics, Inc., San Jose, Calif. being an example.
As is well understood by those skilled in the art, one important feature of a logic analyzer is its ability to capture data from the system under test and to present it in a form which provides a representation of the operation of the system under test. The sophisticated structure of present day microprocessor systems demands that the capability of monitoring this flow of information augmented by an ability to focus this view around a specific area of processor code or a sequence of words or events. Consequently, a desirable logic analyzer feature is the ability to trap or trace data around a very specific system event.
In practical terms, this trapping feature is implemented by providing a logic analyzer with a word recognition ability and designing it to react to word recognition in a variety of ways. For example, Tarczy-Hornoch U.S. Pat. No. 4,241,416 describes an analyzer which can capture and display data which precedes or follows the occurrence of a recognized data word. This is extremely useful for debugging software routines because it provides the user with the ability to view program activity immediately before or after a system cycle of interest. For example, a system malfunction may be characterized by the sporadic production from an I/O port of data whose value is not known, but which is suspected to be incorrect. In this case the activity of the port, which is irregular, is required to be monitored, preferably by identification of the port's address. The Tarczy-Hornoch analyzer has the ability to recognize the I/O port address and display a selected number of system cycles which precede that address. This enables the user to inspect the opcodes and their associated addresses occurring before the I/O cycle of interest to determine whether a valid command preceded it. However, this analyzer only has the capability of holding one set of captured data at a time; a subsequent capture will cancel a previous the capture. Hence, the user must interact with the system under test by stepping through its program, segment by segment, until the incorrect opcode address is discovered.
Another problem with a logic analyzer which can capture and hold only one group of data bus words at a time is that the user must spend his time setting it up to respond to the precise point in a software program where the processor system malfunctions. In the example cited above where the I/O activity may occur repeatedly throughout the program without every occurrence representing a malfunction, a design engineer can consume a significant amount of time in configuring the analyzer to respond to only the pathological occurrence.
It is therefore desirable to provide a logic analyzer with the ability to acquire a plurality of groups of data from a system under test, with each group containing a particular data cycle and the data occurring just before and contiguous with the cycle of interest. The acquisition of such groups during the course of the program will provide a system designer with a powerful tool for analyzing software execution with as few as one complete and uninterrupted runthrough of the program.
Logic analyzers which can store a plurality of data groups are known, an example being the PM 3551 logic analyzer manufactured by Philips Gloeilampenfabrieken N.V., Eindhoven, Netherlands. However, the data word groups acquired by the Philips analyzer include data which occurs after, rather than before, the data cycle on which capture is keyed. This does permit the analyzer to key data group capture upon a data word which stimulates a word of interest. However, in order to accumulate all occurrences of the word, the user must know every possible opcode which can call or stimulate it. Therefore, not only must the designer know all possible stimuli of a data cycle, but the logic analyzer must have the ability to recognize and react to all of them simultaneously. It is evident that, for this type of logic analyzer, as the number of cycles of interest increases, so too, and at a higher rate, does the number of stimulus words which must be identified and stored. Thus, where a user may wish to analyze system activity around more than one cycle of interest, the logic analyzer must have a significant capacity for recognizing the stimulus signals.
Therefore, it is desirable to provide a logic analyzer with the ability to store a plurality of groups of signals, with each group containing a data word of interest and a number of words which precede it on a data bus. This feature will eliminate the tedious operation and the limitation of single-shot acquisition of analyzers represented by the Tarczy-Hornoch device and reduce the user time required for their operation, while at the same time eliminating the word recognition limitations imposed by the Phillips-type analyzer.